With the development of a semiconductor technology and a mounting technology on a chip, an apparatus (for example, an apparatus so-called a blade server) is provided, in which a plurality of CPUs and a main memory having a large capacity are mounted on one board. In such apparatus, because of a problem of the mounting, it is difficult to arrange a plurality of modules (or chips) in a same distance as other modules (or chips). Thus, a time varies when an LSI chip, which is a data request source, receives data from the other LSI chip, which is a data request destination. This time variation mainly depends on characteristics of a board wiring and characteristics of a connector, and performance of the LSI chip. With an improvement of a data processing speed in the recent years, a width of the time variation also becomes unnegligible.
To suppress the EMI (unnecessary Electromagnetic Interference) within the standards, a signal line control method is proposed, which measures a driver output current detected by using a current sensing unit in a driver, and controls the measured output current (for example, refer to Patent Document 1).
However, the control for the driver output current by the above signal line control method is a current control just in the driver. Then, the characteristics of the board wiring, the characteristics of the connector, and the time variation to a reception apparatus are not considered. Thus, the current adjustment cannot make an input level of the receiver become well.
For example, data is transmitted from one LSI, which has a driver, to another LSI, which is an external load, as described by referring to FIGS. 10 and 11. In this case, the data transmission is executed in a state that a number of PMOS driving stages is fixed in the driver, and a number of NMOS driving stages is fixed in the driver.
FIG. 10 is a diagram illustrating a conventional exemplary structure when data is transmitted and received between LSIS. A transmission LSI 3 has a driver 30. The transmission LSI 3 is connected to a reception LSI 4 through a board wiring 5 and the like. The driver 30 has a plurality of driving elements (for example, buffers) 31 to 33. As illustrated in FIG. 11, each of driving elements 31 to 33 includes a CMOS circuit, which has a PMOS transistor 200 and an NMOS transistor 201. FIG. 11 illustrates an exemplary structure of the driving element 31 in FIG. 10. Each of driving elements 31 to 33 outputs a current in response to a level of a driver input. In the conventional technology illustrated in FIGS. 10 and 11, the number of the PMOS driving stages is fixed in the driver 30, and the number of the NMOS driving stages is fixed in the driver 30.
When data is transmitted from the transmission LSI 3 to the reception LSI 4, first, a driver input is inputted to the driver 30, which has a plurality of the above driving elements. In response to the driver input, the driver 30 outputs a current. The current outputted from the driver 30 is inputted to a receiver 41, which is a semiconductor circuit included in the reception LSI 4, through the board wiring 5. The receiver 41 outputs a receiver output, so that the reception LSI 4 receives the data.
Patent Document 1: Japanese Patent No. 3520913
In the conventional technology illustrated in FIGS. 10 and 11, the number of the driving stages of PMOS transistors is fixed, and the number of the driving stages of NMOS transistors is fixed. Thus, even when a change of the output current from the driver 30 is increased because of a variation of the current characteristics of each of driving elements 31 to 33, the output current cannot be adjusted. When the output current, whose change is increased, is inputted from the driver 30 to the receiver 41 of the reception LSI 4 through the board wiring 5, a change of voltage amplitude of the data is increased in the receiver 41.